1. Field of the Invention
The present invention relates to circuitry for use in electronic systems having portions operating at different clock frequencies. More particularly, the present invention relates to circuitry for generating clock signals of varying frequency for use by different components or sub-components within processor systems.
2. Art Background
Computer systems and other microprocessor controlled systems are often divided into groups of functionally related components which have a common clock line carrying a signal that varies at a predetermined frequency. The various components in the computer system receive the clock signal and typically carry out their operations during one or more clock cycles.
In some prior art systems, all major components operate at the frequency of the clock signal; however, more advanced systems often use multiple operating frequencies to improve the throughput of individual functional units. For example, a processor may have a bus interface that operates at one-half, one-third, or some other multiple of the processor operating frequency. A fractional speed memory interface is often necessary because bus drivers may not be able to drive interconnect lines external to the individual integrated circuit at the processor operating frequency. Despite being integrated into the same package, module, or even the same die, some portions of circuitry still may not be able to operate in lock-step with others and thus require separate clock signals.
One common aim in designing a multiple clock system is to avoid clock skew. Skew refers to the phase difference between a reference clock and the clock signal seen by each of the components. This phase difference may occur due to non-uniform propagation delays in the circuitry and routing. As clock frequencies increase, the allowable skew must decrease to allow the same percentage of each clock period for signal propagation.
A phase locked loop (PLL) is a circuit often used for clock generation where low clock skew is desired. A PLL utilizes a voltage controlled oscillator (VCO) and a phase comparator to match the phase of the PLL output to that of a reference clock. This arrangement can perform frequency multiplication by using a counter or a divider in the feedback path for the PLL output. Such a technique, however, can generate only whole multiples of the input clock frequency.
In those computer and microprocessor systems where some components operate at a slower clock frequency than the reference clock, a division of the clock frequency is needed. One odd division technique that may achieve a fifty percent duty cycle doubles the frequency (using the PLL based multiplication scheme described above) and then divides by twice the value of the desired odd divisor. A more elaborate scheme using a divider in conjunction with a PLL/VCO loop may be used to achieve clock multiplication by any fraction D/N. Unfortunately, such implementations utilize a phase locked loop and other analog circuitry which adds expense and complexity to an integrated circuit.
Digital division circuits, on the other hand, are often limited to division by even integers. Some digital dividers which are capable of odd division generate a clock signal that varies from a fifty percent duty cycle by one half of a clock cycle because odd division with a fifty percent duty cycle requires alternately aligning the generated clock to the rising and falling edges of the input clock. Other prior art digital dividers which are capable of odd division and do generate clock signals accurate to the proper half cycle still may compromise their duty cycle symmetry by using different clock signals to generate rising and falling edges or by using uneven numbers of gates in the logical paths which generate the rising and falling edges of the output clock.
As interconnect lengths decrease and the clock frequencies increase, the need to minimize clock skew may rise. The receiving hardware also often relies on even duty cycles to perform necessary tasks and meet stringent timing requirements. Consequently, closer control over the relative timing between the original and divided down clocks than provided by the prior art may be necessary in order to provide sufficient time for communication between devices and to reduce the time reserved as guardband.
Additionally, prior art techniques are often limited to one phase relationship between the input and generated clock signals. In other words, one edge of the generated clock signal is limited to being aligned with a specific edge of the input clock signal. While an inverter could be added in such designs to get the opposite polarity, the versatility of choosing polarity during operation is not available. Moreover, further increasing gates counts or logic between the clock controlled gates and the clock output produces further undesirable skew variations since each circuitry element introduces a delay which may vary over temperature and operating conditions.
Thus, the prior art fails to provide fifty percent duty cycle clock division circuitry which adequately addresses the needs of high performance computer systems. Some prior art systems require complex analog circuitries to effectuate such division. Others accomplish such division using digital circuitry, but may not provide adequate skew, polarity, and phase control.